6-163 description hewlett-packards ina-54063 is a silicon monolithic amplifier that offers excellent gain and power output for applications to 3.0 ghz. packaged in an ultra- miniature sot-363 package, it requires half the board space of a sot-143 package. with its wide bandwidth and high linearity, the ina-54063 is an excellent candidate for dbs if applications. it also features a unique gain curve which in- creases over the range from 1 to 2 ghz. this gain slope compen- sates for the gain rolloff found in typical receiver systems. the ina-54063 is fabricated using hps 30 ghz f max isosat? silicon bipolar process which uses nitride self-alignment submicrometer lithography, trench isolation, ion implantation, gold metalization, and polyimide intermetal dielectric and scratch protection to achieve superior performance, uniformity, and reliability. 3.0 ghz low noise silicon mmic amplifier technical data ina-54063 features ? ultra-miniature package ? single 5 v supply (29 ma) ? 21.5 db gain (1.9 ghz) ? 8.0 dbm p 1db (1.9 ghz) ? positive gain slope ? unconditionally stable applications ? if amplifier for dbs downconverter, cellular, cordless, special mobile radio, pcs, ism, and wireless lan applications surface mount package sot-363 (sc-70) pin connections and package marking note: package marking provides orientation and identification. output and v d gnd 54 gnd gnd input 1 2 3 6 5 4v cc equivalent circuit (simplified) rf input ground rf output and v d v d 5965-5364e
6-164 ina-54063 absolute maximum ratings absolute symbol parameter units maximum [1] v d supply voltage, to ground v 12 p in cw rf input power dbm 13 t j junction temperature c 150 t stg storage temperature c -65 to 150 thermal resistance [2] : q j-c = 165 c/w notes: 1. operation of this device above any one of these limits may cause permanent damage. 2. t c = 25 c (t c is defined to be the temperature at the package pins where contact is made to the circuit board). electrical specifications, t c = 25 c, z o = 50 w , v d = 5 v, unless noted symbol parameters and test conditions units min. typ. max. std. dev. [1] g p power gain (|s 21 | 2 ) f = 1900 mhz db 19 21.5 0.7 nf noise figure f = 1900 mhz db 5.0 0.4 p 1db output power at 1 db gain compression f = 1900 mhz dbm 8.0 ip 3 third order intercept point f = 1900 mhz dbm 17 f = 2150 mhz 15.7 vswr in input vswr f = 1900 mhz 1.4 vswr out output vswr f = 1900 mhz 2.4 i d device current ma 29 36 1.8 t d group delay f = 1900 mhz ps 272 note: 1. standard deviation number is based on measurement of at least 500 parts from three non-consecutive wafer lots during the initial characterization of this product, and is intended to be used as an estimate for distribution of the typical specification.
6-165 ina-54063 typical performance t c = 25 c, z o = 50 w , v d = 5 v, unless noted figure 7. input and output vswr vs. frequency. 0.3 0.9 1.2 1.5 1.8 0.6 2.1 2.7 2.4 3 0.3 0.9 1.2 1.5 1.8 0.6 2.1 2.7 2.4 3 0.3 0.9 1.2 1.5 1.8 0.6 2.1 2.7 2.4 3 0.3 0.9 1.2 1.5 1.8 0.6 2.1 2.7 2.4 3 frequency (ghz) figure 1. gain vs. frequency and voltage. 10 15 20 25 gain (db) frequency (ghz) figure 4. gain vs. frequency and temperature. 10 14 12 18 16 20 22 gain (db) frequency (ghz) figure 2. noise figure vs. frequency and voltage. 3 5 4 6 8 7 noise figure (db) frequency (ghz) figure 3. output power for 1 db gain compression vs. frequency and voltage. 0 8 4 12 16 p 1 db (dbm) t a = +85 c t a = +25 c t a = ?0 c figure 5. noise figure vs. frequency and temperature. noise figure (db) 6 v 5 v 4 v 6 v 5 v 4 v 4 v 6 v 5 v figure 6. output power for p 1db gain compression vs. frequency and temperature. 0 4 2 8 6 10 14 12 p 1 db (dbm) t a = +85 c t a = +25 c t a = ?0 c 0.3 0.9 1.2 1.5 1.8 0.6 2.1 2.7 2.4 3 frequency (ghz) 0 1 0.5 2 1.5 2.5 3 vswr 0.3 0.9 1.2 1.5 1.8 0.6 2.1 2.7 2.4 3 frequency (ghz) 0.3 0.9 1.2 1.5 1.8 0.6 2.1 2.7 2.4 3 frequency (ghz) 3 4 3.5 5 4.5 5.5 7.5 6 6.5 7 t a = +85 c t a = +25 c t a = ?0 c figure 8. supply current vs. voltage and temperature. i d (ma) 02345 167 v d (v) 0 10 5 20 15 25 45 30 35 40 t a = +85 c t a = +25 c t a = ?0 c vswr out vswr in
6-166 ina-54063 typical scattering parameters [1] , t c = 25 c, z o = 50 w , v d = 5.0 v freq. s 11 s 21 s 12 s 22 k ghz mag. ang. db mag. ang. db mag. ang. mag. ang. factor 0.10 0.11 91 16.9 7.02 19 -27.7 0.04 21 0.47 75 1.50 0.20 0.09 64 17.6 7.56 2 -27.1 0.04 7 0.35 34 1.47 0.30 0.08 51 17.7 7.71 -7 -27.0 0.04 0 0.32 10 1.46 0.40 0.09 42 17.9 7.81 -14 -27.1 0.04 -5 0.31 -7 1.46 0.50 0.08 46 18.1 8.00 -21 -27.3 0.04 -9 0.30 -23 1.47 0.60 0.09 39 18.2 8.11 -27 -27.5 0.04 -12 0.30 -36 1.47 0.70 0.09 32 18.3 8.24 -33 -27.8 0.04 -15 0.31 -47 1.48 0.80 0.09 22 18.5 8.41 -39 -28.1 0.04 -17 0.33 -56 1.48 0.90 0.10 13 18.7 8.58 -45 -28.4 0.04 -19 0.34 -65 1.48 1.00 0.10 5 18.9 8.80 -51 -28.8 0.04 -21 0.35 -73 1.48 1.10 0.11 -3 19.1 9.05 -57 -29.2 0.03 -23 0.37 -80 1.48 1.20 0.11 -11 19.4 9.28 -64 -29.6 0.03 -25 0.38 -88 1.50 1.30 0.12 -20 19.6 9.58 -70 -30.1 0.03 -26 0.39 -94 1.50 1.40 0.12 -29 19.9 9.88 -78 -30.6 0.03 -27 0.40 -101 1.52 1.50 0.13 -36 20.2 10.19 -85 -31.1 0.03 -28 0.41 -108 1.54 1.60 0.14 -44 20.4 10.51 -93 -31.5 0.03 -29 0.41 -114 1.55 1.70 0.15 -53 20.7 10.86 -101 -32.0 0.03 -30 0.42 -120 1.57 1.80 0.16 -61 21.0 11.16 -111 -32.7 0.02 -31 0.42 -126 1.63 1.90 0.17 -68 21.1 11.36 -120 -33.5 0.02 -31 0.41 -132 1.74 2.00 0.20 -73 21.2 11.44 -130 -34.2 0.02 -29 0.40 -138 1.87 2.10 0.22 -80 21.2 11.43 -141 -34.9 0.02 -29 0.38 -144 2.04 2.20 0.24 -89 21.0 11.25 -152 -35.6 0.02 -28 0.37 -148 2.22 2.30 0.26 -99 20.7 10.86 -164 -36.0 0.02 -27 0.35 -151 2.41 2.40 0.27 -108 20.1 10.16 -175 -36.8 0.01 -26 0.34 -155 2.82 2.50 0.28 -112 19.5 9.39 175 -37.8 0.01 -24 0.32 -158 3.42 2.60 0.29 -117 18.6 8.55 166 -39.0 0.01 -23 0.31 -162 4.31 2.70 0.30 -124 17.8 7.79 157 -39.3 0.01 -15 0.29 -164 4.94 2.80 0.30 -130 16.9 7.03 150 -39.6 0.01 -16 0.28 -166 5.69 2.90 0.30 -133 16.1 6.35 144 -41.6 0.01 -15 0.26 -170 8.05 3.00 0.30 -136 15.3 5.83 138 -42.5 0.01 -5 0.25 -171 9.80 3.10 0.31 -138 14.6 5.35 132 -43.7 0.01 3 0.23 -173 12.33 3.20 0.31 -140 13.8 4.92 127 -45.4 0.01 13 0.22 -174 16.36 3.30 0.31 -142 13.2 4.57 121 -45.4 0.01 31 0.21 -174 17.56 3.40 0.31 -143 12.5 4.23 116 -45.7 0.01 47 0.20 -174 19.78 3.50 0.32 -145 11.9 3.93 111 -44.8 0.01 65 0.19 -174 19.14 3.60 0.32 -147 11.2 3.65 106 -43.4 0.01 75 0.19 -174 17.63 3.70 0.33 -148 10.6 3.38 101 -42.2 0.01 82 0.18 -174 16.53 3.80 0.34 -149 9.9 3.11 96 -41.1 0.01 88 0.18 -175 15.72 3.90 0.35 -152 9.1 2.84 92 -40.3 0.01 93 0.17 -175 15.60 4.00 0.35 -156 8.4 2.62 89 -39.3 0.01 99 0.16 -174 15.11 4.10 0.34 -159 7.8 2.46 85 -38.0 0.01 103 0.14 -171 14.09 4.20 0.33 -161 7.1 2.27 79 -37.6 0.01 104 0.13 -156 14.64 4.30 0.32 -161 5.6 1.91 75 -37.6 0.01 112 0.19 -135 17.07 4.40 0.33 -161 4.5 1.68 81 -35.8 0.02 127 0.31 -150 14.81 4.50 0.34 -162 4.8 1.73 82 -33.4 0.02 129 0.33 -170 10.72 4.60 0.35 -166 4.9 1.75 80 -31.7 0.03 128 0.32 180 8.78 4.70 0.35 -170 4.8 1.74 76 -30.4 0.03 126 0.30 173 7.69 4.80 0.33 -173 4.6 1.69 72 -29.3 0.03 124 0.30 167 7.09 4.90 0.34 -174 4.2 1.62 69 -28.2 0.04 123 0.29 164 6.57 5.00 0.34 -177 3.9 1.57 66 -27.2 0.04 122 0.29 160 6.04 note 1 : reference plane per figure 14 in applications information section.
6-167 ina-54063 applications information introduction the ina-54063 is a silicon rfic amplifier that is designed with an internal resistive feedback network to provide a 50 w input and near 75 w output impedance. with a 1-db compressed output power of 8 dbm and noise figure of 5 db, the ina-54063 is well suited for amplifier applications requiring high dynamic ranges. a unique feature of the ina-54063 is a positive gain slope over the 1C2 ghz range that is useful in many satellite-based tv and datacom systems. when used for the if amplifier, the up-slope in the gain of the ina-54063 is intended to compensate for the negative gain slope in many low noise block downconverters (lnb) used in consumer and commercial tv delivery systems, such as dds, dbs, and tvro. the positive gain slope can also compensate for the high fre- quency attenuation characteris- tics of 75 w cables used to connect the outdoor lnbs to indoor set-top converters. in addition to use in tv delivery systems, the ina-54063 will find many applications in 50 w input- 50 w output gain and buffer stages in wireless communica- tions systems. operating details the ina-54063 is a voltage biased device that operates from a +5 volt power supply with a typical current drain of 29 ma. all bias regulation circuitry is integrated into the rfic. figure 9 shows a typical imple- mentation of the ina-54063. the supply voltage for the ina-54063 must be applied to two terminals, the v cc pin and the rf output pin. rf input rfc v d c block c bypass c block rf output 54 figure 9. basic amplifier application. the v d connection to the ampli- fier is rf bypassed by placing a capacitor to ground near the v d pin of the amplifier package. the power supply connection to the rf output pin is achieved by means of an rf choke (inductor). the value of the rf choke must be large relative to 50/75 w in order to prevent loading of the rf output. the supply voltage end of the rf choke is bypassed to ground with a capacitor. if the physical layout permits, this can be the same bypass capacitor that is used at the v d terminal of the amplifier. blocking capacitors are normally placed in series with the rf input and the rf output to isolate the dc voltages on these pins from circuits adjacent to the amplifier. the values for the blocking and bypass capacitors are selected to provide a reactance at the lowest frequency of operation that is small relative to 50 w . example layout for 50 w amplifier an example layout for an ampli- fier using the ina-54063 with 50 w input and 50 w output is shown in figure 10. input output ina-5xx63 demo board 05/95 vcc h figure 10. rf layout for 50 w input and output. this example uses a microstripline design (solid groundplane on the back side of the circuit board). the circuit board material is 0.031-inch thick fr-4. plated through holes (vias) are used to bring the ground to the top side of the circuit where needed. multiple vias are used to reduce the inductance of the path to ground. figure 11 shows an assembled amplifier. the +5 volt supply (v cc ) is fed directly into the v d pin of the ina-54063 and into the rf output pin through the rf choke (rfc). capacitor c3 provides rf bypassing for both the v d pin and the power supply end of the rfc.
6-168 0.50 1.00 1.25 1.50 1.75 0.75 2.00 2.25 2.50 frequency (ghz) -20 -12 -14 -16 -18 -8 output input -10 0 -2 -4 -6 return loss (db) figure 13. measured input and output return loss for 50 w example amplifier. pcb materials typical choices for pcb material for low cost wireless applications are fr-4 or g-10 with a thickness of 0.025 or 0.031 inches. a thickness of 0.062 inches is the maximum that is recommended for use with this particular device. the use of a thicker board material increases the inductance of the plated through vias used for rf grounding and may deteriorate circuit performance. adequate grounding is needed not only to obtain maximum amplifier performance but also to reduce any possibility of instability. phase reference planes the positions of the reference planes used to measure s-param- eters for this device are shown in figure 14. as seen in the illustra- tion, the reference planes are located at the point where the package leads contact the test circuit. test circuit reference planes figure 14. phase reference planes. figure 11. assembled 50 w amplifier. input c1 c3 c2 c4 rfc output ina-5xx63 demo board 05/95 vcc h 54 capacitor c4 is optional and may be used to add additional bypass- ing for the v cc line. a well by- passed v cc line is especially necessary in cascades of ampli- fier stages to prevent oscillation that may occur as a result of rf feedback through the power supply lines. for this demonstration circuit, the value chosen for the rf choke was 220 nh (coilcraft 1008cs-221 or equivalent). all of the blocking and bypass capaci- tors are 1000 pf. these values provide excellent amplifier performance from under 50 mhz through 2.5 ghz. larger values for the choke and capacitors can be used to extend the lower end of the bandwidth. since the gain of the ina-54063 extends down to dc, the frequency response of the amplifier is limited only by the values of the capacitors and choke. a convenient method for making rf connection to the demonstra- tion board is to use a pcb mount- ing type of sma connector (johanson 142-0701-881, or equivalent). these connectors can be slipped over the edge of the pcb and the center conduc- tors soldered to the input and output lines. the ground pins of the connectors are soldered to the ground plane on the backside of the board. the extra ground pins for the top of the board are not needed and are clipped off. the measured test results for the 50 w input/output example amplifier using the ina-54063 are shown in figures 12 and 13. 0.50 1.00 1.25 1.50 1.75 0.75 2.00 2.25 2.50 frequency (ghz) 0 10 5 15 25 20 gain (db) figure 12. measured gain of 50 w example amplifier.
6-169 sot-363 pcb layout the ina-54063 is packaged in the miniature sot-363 (sc-70) surface mount package. a pcb pad layout for the sot-363 package is shown in figure 15 (dimensions are in inches). this layout provides ample allowance for package placement by auto- mated assembly equipment without adding pad parasitics that could impair the high frequency performance of the ina-54063. the layout is shown with a nominal sot-363 package foot- print superimposed on the pcb pads for reference. 0.026 0.035 0.075 0.016 figure 15. pcb pad layout for ina-54063 (dimensions in inches). statistical parameters several categories of parameters appear within this data sheet. parameters may be described with values that are either minimum or maximum, typi- cal, or standard deviations. the values for parameters are based on comprehensive product characterization data, in which automated measurements are made on of a minimum of 500 parts taken from 3 non-consecu- tive process lots of semiconduc- tor wafers. the data derived from product characterization tends to be normally distributed, e.g., fits the standard bell curve. parameters considered to be the most important to system perfor- mance are bounded by minimum or maximum values. for the ina-54063, these parameters are: power gain (|s 21 | 2 ), noise figure (nf), and device current (i d ). each of these guaranteed param- eters is 100% tested. values for most of the parameters in the table of electrical specifi- cations that are described by typical data are the mathematical mean ( m ), of the normal distribu- tion taken from the characteriza- tion data. for parameters where measurements or mathematical averaging may not be practical, such as s-parameters or noise parameters and the performance curves, the data represents a nominal part taken from the center of the characterization distribution. typical values are intended to be used as a basis for electrical design. to assist designers in optimizing not only the immediate circuit using the ina-54063, but to also optimize and evaluate trade-offs that affect a complete wireless system, the standard deviation ( s ) is provided for many of the electrical specifications param- eters (at 25 c) in addition to the mean. the standard deviation is a measure of the variability about the mean. it will be recalled that a normal distribution is completely described by the mean and standard deviation. standard statistics tables or calculations provide the probabil- ity of a parameter falling between any two values, usually symmetri- cally located about the mean. referring to figure 16 for ex- ample, the probability of a parameter being between 1 s is 68.3%; between 2 s is 95.4%; and between 3 s is 99.7%. 68% 95% 99% parameter value mean ( ), typ -3 s -2 s -1 s +1 s +2 s +3 s figure 16. normal distribution. smt assembly reliable assembly of surface mount components is a complex process that involves many material, process, and equipment factors, including: method of heating (e.g., ir or vapor phase reflow, wave soldering, etc.) circuit board material, conductor thickness and pattern, type of solder alloy, and the thermal conductivity and thermal mass of components. components with a low mass, such as the sot-363 package, will reach solder reflow temperatures faster than those with a greater mass. the ina-54063 is has been qualified to the time-temperature profile shown in figure 17. this profile is representative of an ir reflow type of surface mount assembly process. after ramping up from room temperature, the circuit board with components attached to it (held in place with solder paste) passes through one or more preheat zones. the preheat zones increase the temperature of the
6-170 board and components to prevent thermal shock and begin evapo- rating solvents from the solder paste. the reflow zone briefly elevates the temperature suffi- ciently to produce a reflow of the solder. the rates of change of tempera- ture for the ramp-up and cool- down zones are chosen to be low enough to not cause deformation of the board or damage to components due to thermal figure 17. surface mount assembly profile. time (seconds) t max temperature ( c) 0 0 50 100 150 200 250 60 preheat zone cool down zone reflow zone 120 180 240 300 shock. the maximum tempera- ture in the reflow zone (t max ) should not exceed 235 c. these parameters are typical for a surface mount assembly process for the ina-54063. as a general guideline, the circuit board and components should be exposed only to the minimum temperatures and times necessary to achieve a uniform reflow of solder. electrostatic sensitivity rfics are electro- static discharge (esd) sensitive devices. although the ina-54063 is robust in design, permanent damage may occur to these devices if they are sub- jected to high energy electrostatic discharges. electrostatic charges as high as several thousand volts (which readily accumulate on the human body and on test equip- ment) can discharge without detection and may result in degradation in performance, reliability, or failure. electronic devices may be subjected to esd damage in any of the following areas: ? storage and handling ? inspection and testing ? assembly ? in-circuit use the ina-54063 is an esd class 1 device. therefore, proper esd precautions are recommended when handling, inspecting, testing, assembling, and using these devices to avoid damage.
6-171 ina-54063 part number ordering information part number devices per container container ina-54063-tr1 3000 7" reel INA-54063-BLK 100 tape strip in antistatic bag package dimensions outline 63 (sot-363/sc-70) 2.20 (0.087) 2.00 (0.079) 1.35 (0.053) 1.15 (0.045) 1.30 (0.051) ref. 0.650 bsc (0.025) 2.20 (0.087) 1.80 (0.071) 0.10 (0.004) 0.00 (0.00) 0.25 (0.010) 0.15 (0.006) 1.00 (0.039) 0.80 (0.031) 0.20 (0.008) 0.10 (0.004) 0.30 (0.012) 0.10 (0.004) 0.30 ref. 10 0.425 (0.017) typ. dimensions are in millimeters (inches)
6-172 tape dimensions and product orientation for outline 63 device orientation user feed direction cover tape carrier tape reel end view 8 mm 4 mm top view 54 54 54 54 p p 0 p 2 f w c d 1 d e a 0 8 max. t 1 (carrier tape thickness) t t (cover tape thickness) 5 max. b 0 k 0 description symbol size (mm) size (inches) length width depth pitch bottom hole diameter a 0 b 0 k 0 p d 1 2.24 0.10 2.34 0.10 1.22 0.10 4.00 0.10 1.00 + 0.25 0.088 0.004 0.092 0.004 0.048 0.004 0.157 0.004 0.039 + 0.010 cavity diameter pitch position d p 0 e 1.55 0.05 4.00 0.10 1.75 0.10 0.061 0.002 0.157 0.004 0.069 0.004 perforation width thickness w t 1 8.00 0.30 0.255 0.013 0.315 0.012 0.010 0.0005 carrier tape cavity to perforation (width direction) cavity to perforation (length direction) f p 2 3.50 0.05 2.00 0.05 0.138 0.002 0.079 0.002 distance width tape thickness c t t 5.4 0.10 0.062 0.001 0.205 0.004 0.0025 0.00004 cover tape
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